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| Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 FEATURES * 4-bit parallel load shift register * Independent 3-State buffer outputs, Q0-Q3 * Separate Qs output for serial expansion * Asynchronous Master Reset DESCRIPTION The 74F395 is a 4-bit Shift Register with serial and parallel synchronous operating modes and 3-State buffer outputs. The shifting and loading operations are controlled by the state of the Parallel Enable (PE) input. When PE is High, data is loaded from the Parallel Data inputs (D0-D3) into the register synchronous with the High-to-Low transition of the Clock input (CP). When PE is Low, the data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and the data in the register is shifted one bit to the right in the direction (Q0!Q1!Q2!Q3) synchronous with the negative clock transition. The PE and Data inputs are fully edge-triggered and must be stable one setup prior to the High-to-Low transition of the clock. The Master Reset (MR) is an asynchronous active-Low input. When Low, the MR overrides the clock and all other inputs and clears the register. The 3-state output buffers are designed to drive heavily loaded 3-State buses, or large capacitive loads. The active-Low Output Enable (OE) controls all four 3-State buffers independent of the register operation. The data in the register appears at the outputs when OE is Low. The outputs are in High impedance "OFF" state, which means they will neither drive nor load the bus when OE is High. The output from the last stage is brought out separately. This output (Qs) is tied to the Serial Data input (Ds) of the next register for serial expansion applications. The Qs output is not affected by the 3-State buffer operation. PIN CONFIGURATION MR Ds D0 D1 D2 D3 PE GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q0 Q1 Q2 Q3 Qs CP OE SF00940 TYPE 74F395 TYPICAL fMAX 120MHz TYPICAL SUPPLY CURRENT (TOTAL) 32mA ORDERING INFORMATION DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F395N N74F395D INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 - D3 Ds PE MR OE CP Qs Q0-Q3 Data inputs Serial data input Parallel Enable input Master Reset input (active Low) Output Enable input (active Low) Clock Pulse input (active falling edge) Serial expansion output Data outputs (3-State) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 150/40 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA 3.0mA/24mA NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state. 1990 Oct 23 1 853-0370 00780 Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 LOGIC SYMBOL 2 3 4 5 6 IEC/IEEE SYMBOL (IEEE/IEC) 1 9 R EN4 M1[LOAD] M2[SHIFT] 10 C3/2! 2,3D 1,3D 1,3D 4 4 14 13 12 11 15 SRG4 Ds 7 10 9 1 PE CP OE MR Q0 D0 D1 D2 D3 7 Qs 11 2 3 Q1 Q2 Q3 4 5 15 VCC = Pin 16 GND = Pin 8 14 13 12 6 SF00941 SF00942 LOGIC DIAGRAM OE CP MR PE 9 10 1 7 Ds 2 CP R S CLR Q D0 3 Q 15 Q0 CP 4 R S CLR Q D1 Q 14 Q1 CP 5 R S CLR Q D2 Q 13 Q2 CP 6 R S CLR Q D3 Q 12 Q3 11 VCC = Pin 16 GND = Pin 8 Qs SF00943 1990 Oct 23 2 Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 MODE SELECT-FUNCTION TABLE INPUTS MR L H H H H # # # CP X # PE X l l h h Ds X l h X X Dn X X X l h Q0 L L H L H OUTPUTS Q1 L q0 q0 L H Q2 L q1 q1 L H Q3 L q2 Shift right q2 L Parallel load H 3-STATE BUFFER OPERATING MODES Read L H H H L H H Z Z H L Disable buffers H REGISTER OPERATING MODES Reset (clear) H = High voltage level h = High voltage level one set-up time prior to the High-to-Low clock transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low clock transition qn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the High-to-Low clock transition X = Don't care Z = High impedance "OFF" state # = High-to-Low clock transition INPUTS OE L Qn (Register) L OUTPUTS Q0, Q1, Q2, Q3 L Qs L ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Qs Current applied to output in Low output state Q0-Q3 Operating free-air temperature range Storage temperature range 48 0 to +70 -65 to +150 mA C C PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +5.5 40 UNIT V V mA V mA RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIK IOH Supply voltage High-level input voltage Low-level input voltage Input clamp current Qs High-level output current Q0-Q3 Qs IOL Tamb Low-level output current Q0-Q3 Operating free-air temperature range 0 24 70 mA C -3 20 mA mA PARAMETER MIN 4.5 2.0 0.8 -18 -1 NOM 5.0 MAX 5.5 V V V mA mA UNIT 1990 Oct 23 3 Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC IOL = MAX 5%VCC LIMITS MIN 2.5 2.7 2.4 2.7 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 50 -50 -60 MR=PE=Dn=Ds=4.5V, OE=GND, CP=# VCC = MAX MR=OE=Dn=Ds=GND, PE=4.5V, CP=# MR=Dn=Ds=GND, OE=4.5V 33 35 32 -150 48 50 46 3.4 TYP2 MAX UNIT V V V V V V V A A mA A A mA mA mA mA Qs VOH High-level output voltage Q0-Q3 VCC = MIN, VIL = MAX, VIH=MIN IOH=-1mA IOH =-3mA VOL VIK II IIH IIL IOZH IOZL IOS Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current High level of voltage applied Off-state output current Low level of voltage applied Short-circuit output current3 ICCH Q0-Q3 only Q0-Q3 only VCC = MIN, VIL = MAX, VIH = MIN, VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX ICC Supply current (total) ICCL ICCZ NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1990 Oct 23 4 Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25C CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to Qn Propagation delay CP to Qs Propagation delay MR to Qn Propagation delay MR to Qs Output Enable time to High or Low level Output Disable time from High or Low level Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 2 Waveform 4 Waveform 5 Waveform 4 Waveform 5 105 3.5 5.0 4.5 5.5 5.0 4.5 4.0 3.5 1.0 1.0 TYP 120 6.0 8.0 6.0 7.5 7.5 7.0 6.5 6.0 2.5 3.5 8.5 11.0 8.5 10.0 10.0 9.0 9.0 8.0 4.5 5.5 3.5 5.0 4.0 5.0 5.0 4.5 4.0 3.5 1.0 1.0 9.5 11.5 9.5 10.5 10.5 9.5 10.0 8.5 5.5 6.5 MAX VCC = +5V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN MAX MHz ns ns ns ns ns ns UNIT AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25C CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tW(H) tW(L) tW(L) tREC Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Setup time, High or Low PE to CP Hold time, High or Low PE to CP CP Pulse width High or Low MR Pulse width Low Recovery time MR to CP Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 1 Waveform 2 Waveform 2 2.5 1.5 1.5 1.5 6.5 6.0 0 0 5.0 4.0 2.5 6.0 TYP MAX VCC = +5V 10% Tamb = 0C to +70C CL = 50pF, RL = 500 MIN 3.0 2.0 1.5 1.5 7.0 6.5 0 0 5.5 4.5 3.0 7.0 MAX ns ns ns ns ns ns ns UNIT 1990 Oct 23 5 Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fMAX CP VM tw(L) tPHL tw(H) CP tPLH tPHL Qn, Qs VM VM Qn, Qs VM VM VM MR VM tw(L) VM tREC SF00944 SF00945 Waveform 1. Propagation Delay, Clock Input to Output, Clock Widths, and Maximum Clock Frequency Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time Dn STABLE VM VM OE ts th STABLE VM VM ts th VM tPZH VM tPHZ VM 0V VOH -0.3V Ds Qn SF00343 PE VM ts VM th VM ts VM th Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level CP VM VM OE VM tPZL VM tPLZ VM SF00946 Waveform 3. Parallel Enable and Data Setup Time and Hold Time Qn VOL +0.3V SF00344 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 1990 Oct 23 6 Philips Semiconductors Product specification 4-bit cascadable shift register (3-State) 74F395 TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V) 90% Test Circuit for 3-State Outputs and Totem-Pole Output (Qs) SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open VM Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns SF00957 1990 Oct 23 7 |
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